Biography of Kemal Ebcioğlu

Activities at the IBM Thomas J. Watson Research Center

Kemal Ebcioğlu conducted research at the IBM Research Division, IBM Thomas J. Watson Research Center, P.O. Box 704, Yorktown Heights, NY 10598, USA, from 1986 to 2005.

Dr. Ebcioğlu's last position at IBM was Research Staff Member and Co-Leader (with Vivek Sarkar), Programming Model and Tools Area (a group of about 40 software researchers inside IBM and in the collaborating universities), as part of IBM's HPCS (High Productivity Computer Systems)/PERCS project. HPCS/PERCS (Power 775) was a DARPA-funded research project for designing a supercomputer, which aimed to simultaneously achieve high performance, high programmer productivity, and commercial viability. Ebcioğlu was a member of the core team that designed and implemented X10, a new high-productivity language for programming supercomputers in a scalable manner. He co-authored early X10 papers, contributed to the HPCS/PERCS project programming productivity research effort (PPHEC-2004, PPHEC-2006), and interacted closely with the teams at all levels of the HPCS/PERCS hardware-software stack.

Ebcioğlu also led numerous projects at the IBM Research Division throughout his career, including the following:

DAISY (Dynamically Architected Instruction Set from Yorktown): Starting in 1996 (RC20538, ISCA-24), Ebcioğlu and the DAISY team developed original techniques to emulate a legacy architecture on a new, highly parallel architecture, with 100% compatibility (including OS code), using a dynamic binary translation approach, with aggressive just-in-time parallelizing transformations. This approach liberates a designer from having to implement a given Instruction Set Architecture verbatim, thus offering hardware simplifications and ample opportunities for innovation, including convergence among multiple architectures. A version of the DAISY software was released as an open-source project, and a related tutorial was given at the MICRO-33 conference.

VLIW: In 1986, Ebcioğlu proposed and launched a new Very Long Instruction Word (VLIW) architecture and compiler research project, which, unlike previous approaches at the time that primarily concentrated on scientific applications, focused on improving the performance of branch-intensive, non-numerical code. The first designs of the IBM Research VLIW architecture already had an essential hardware feature for aggressively parallelizing branch-intensive code: the correct handling of exceptions in the presence of speculative execution (such as a 33rd bit (exception tag bit) in registers, an interruptible (exception-raising) and an uninterruptible variant of each operation, as well as the ability to force speculatively executed memory-mapped I/O operations into no-ops, to prevent harmful side effects). Sub-projects of the IBM Research VLIW effort included:

• A hardware prototype of a VLIW machine, capable of executing 8 ALU operations, 4 loads/stores and 7 conditional branches per cycle, achieved through an efficient parallel hardware implementation of:
  • Multi-way branching with arbitrary decision tree-shaped VLIW instructions, including tree path-specific conditional execution of ALU and memory operations, and
  • Techniques (for the technology of the day) for highly parallel accesses to registers and memory.
• Object code translation technology, including hardware-software solutions for aggressively re-ordering operations (including moving loads above prior store operations even when address overlap cannot be disproved at compile time), in the presence of self-modifying code, precise exceptions, and multiprocessor memory consistency (also see ICS-92).
• Novel compilation techniques for extracting parallelism from branch intensive, integer code. Unlike trace scheduling, these compiler techniques can schedule operations on multiple paths as soon as their operands and ready, but will stop executing the remaining operations on a given path as soon as it is known that that path will not be taken. They can recognize common computations on multiple paths and execute them only once. They can also achieve variable iteration initiation intervals during software pipelining of loops with conditional branches. Three generations of parallelizing compilers were designed throughout the project.
• Scalable VLIW architectures, where each VLIW is represented by a variable-length group of RISC instructions including conditional branches, thus remaining compatible with a standard RISC ISA and tolerating differences among the implementations of an architecture (ICCD-90, US Patent 5721854, ForestaPC).
• Use of VLIW compilation techniques to improve performance of existing superscalars. The VLIW team's compiler techniques and OS enhancements were integrated in IBM's compiler product for RISC processors, and in AIX, and helped obtain significant improvements in SPECint benchmarks in the September 1993 announcement of IBM's POWER-2, RS/6000 and POWERPC 601 products. The IBM POWER-2 became the world's highest performance processor on SPECint as of September 1993.

CHORAL: This project was based on Ebcioğlu's doctoral dissertation at the State University of New York/Buffalo ('An Expert System for Harmonization of Chorales in the Style of J.S. Bach'). Although algorithmic composition of music (in particular, of non avant-garde music) is a controversial topic, Ebcioğlu proposed an approach to create a simple form of tonal music (chorale harmonizations in the style of J.S. Bach) with a computer algorithm, based on simultaneously following all three of the following principles:

• Programming a comprehensive amount of knowledge about the desired musical style,
• Using rigorous constraints to impose high musical quality and to rule out unacceptable solutions, efficiently utilizing a computer's power for search and backtracking,
• Using many style-specific heuristics to prioritize the algorithm's choices when extending a partially created composition, given that rigorous constraints are not by themselves enough to generate beautiful music.

Dr. Ebcioğlu received 2 IBM Outstanding Technical Achievement Awards (for "CHORAL: An Expert System Application for Harmonizing Music" and for "Very Long Instruction Word Compiler Optimization Technologies," respectively). He received an IBM Divisional award for contributions to POWER-2 performance. He received an IBM Research Division Technical Group Award, for contributions to Phase I of the HPCS/PERCS project. He is a co-inventor of 14 US patents awarded to IBM. LaTTe, a Java JIT compiler and JVM project with innovations in fast register allocation, thread synchronization, exception handling, just-in-time optimizations, just-in-time instruction scheduling, and garbage collection, was realized through the collaboration of Ebcioğlu's team at IBM Research and Seoul National University. Ebcioğlu also contributed to IBM's Océano project for dynamic provisioning of servers in an e-business environment, and to numerous strategy task forces while at IBM.

Previous Work Experience

1979-1986

Nanodata (Intellitek) Computer Corporation, One Computer Park, Buffalo, NY 14203, USA. Last position: Senior System Designer. Ebcioğlu achieved performance improvements in customer applications by re-writing the horizontal microcode for the QMX, an IBM S/370 plug-compatible machine, and by re-writing the horizontal microcode and re-designing the hardware for three boards for the QM-1, a user microprogrammable computer with a 360-bit instruction word. Ebcioğlu also proposed, designed the hardware for, and wrote a C compiler for the QM-32, a RISC-style stack machine capable of single-cycle operation execution and zero overhead branching, subroutine call, and return.

1976-1979

State Opera and Ballet, Ankara, Turkey. Pianist.

1974-1976

Ankara State Conservatory, Turkey. Solfège Instructor.

Professional Activities

• Received the IEEE Computer Society B. Ramakrishna Rau Award in 2013, which is presented in recognition of substantial contributions in the field of computer microarchitecture and compiler code generation. The award was presented "for contributions to VLIW, instruction-level-parallelism, binary translation,Java performance, and service to the community" (Speech at MICRO-46, December 2013).
• SIGMICRO Distinguished Service Award, 2014.
• IFIP Silver Core Award, 2007.
• Three best paper awards:
  • IEEE/ACM MICRO-22, 1989. Combining as a Compilation Technique for VLIW Architectures. Co-author: Toshio Nakatani.
  • IEEE/ACM MICRO-23, 1990. Using a Lookahead Window in a Compaction-Based Parallelizing Compiler. Co-author: Toshio Nakatani.
  • ACM PLDI-2005. Programming by Sketching for Bit-Streaming Programs. Co-authors: Armando Solar-Lezama, Rodric Rabbah, Rastislav Bodik.
• Received the ACM SIGPLAN 2015 Most Influential OOPSLA Paper Award, for the 2005 ACM SIGPLAN OOPSLA paper X10: An Object-Oriented Approach to Non-Uniform Cluster Computing. Co-authors: Philippe Charles, Christian Grothoff, Vijay Saraswat, Christopher Donawa, Allan Kielstra, Christoph von Praun, Vivek Sarkar.
• More than 70 technical publications.
• ACM SIGMICRO Chair, 1999-2005.
• IFIP (International Federation of Information Processing) Working Group 10.3 (Concurrent Systems):
  • Vice Chair for North America, 1996-2001.
  • Chair, 2001-2006.
• IEEE Senior Member, 2000-present.
• Associate Editor, IEEE Transactions on Computers, 2000-2004.
• Associate Editor, ACM Transactions on Architectures and Code Optimization, 2003-2008.
• Advisory Board Member, IEEE Micro, 2006-present.
• Editorial Board Member, Parallel Processing Letters, 2001-2016.

Conference Activities

• Co-founded the Parallel Architectures and Compilation Techniques Conference (PACT), currently co-sponsored by IFIP, ACM and IEEE Computer Society.
• General Chair, Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism (a precursor of the PACT conference series), Orlando, Florida, USA, 20-22 January 1993.
• Program Committee Chair, 28th Annual International IEEE/ACM Symposium on Microarchitecture (MICRO-28), December 1995, Ann Arbor, Michigan.
• Program Committee Chair, Parallel Architectures and Compilation Techniques Conference 1998 (PACT-98), October 1998, Paris, France.
• PACT Conference Steering Committee Chair, 2000-2001.
• General Chair, 16th Annual ACM International Conference on Supercomputing 2002 (ICS-02), New York City, New York, June 2002.
• General Chair, 35th Annual International IEEE/ACM Symposium on Microarchitecture (MICRO-35), November 2002, Istanbul, Turkey.
• Program Committee Vice-Chair for Architectures, International Parallel and Distributed Processing Symposium 2005 (IPDPS 2005), Denver, Colorado, April 2005.
• Co-founder and Steering Committee Chair, 2004-2022, IFIP International Conference on Network and Parallel Computing (NPC), organized annually since 2004.
• Steering Committee Chair, PACT Conference, 2012-2022.
• General Co-Chair, 20th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, (ASPLOS 2015), March 2015, Istanbul, Turkey.
• Organizing Committee Member of the first three Workshops on Artificial Intelligence and Music. The first workshop was held in August 1988, in St. Paul, MN (with AAAI-88); the second one was held in August 1989, in Detroit, MI (with IJCAI-89); and the third was held in August 1990, in Stockholm, Sweden (with ECAI-90).

Ebcioğlu also served on the program committees and steering committees of many conferences (e.g., MICRO, PACT, HPCA, PLDI, ICS, Euro-par, Computing Frontiers). He served on National Science Foundation panels, and on the National Science Foundation Committee of Visitors.

Education

• Doctor of Philosophy, Department of Computer Science, S.U.N.Y. at Buffalo, 1986. Dissertation title: An Expert System for Harmonization of Chorales in the Style of J.S. Bach (artificial intelligence research). Advisor: John Myhill.
• Master of Science, Department of Computer Engineering, Middle East Technical University, Ankara, Turkey, 1979. Thesis title: Strict Counterpoint: A Case Study in Musical Composition by Computers. Advisor: Müren Gökeri.
• Master of Music, Advanced Composition Department (Komposizyon Bölümü İleri Yüksek Devre), Ankara State Conservatory, Turkey, 1977. Composition Teacher: Necil Kazım Akses.
• Bachelor of Arts (Lisans), Department of French and Romance Languages and Literatures, Faculty of Letters, Istanbul University, Turkey, 1974. Thesis Title: Étude du Champ Notionnel du Léxème Original. Advisor: Süheyla Bayrav.

Musical Compositions

Ebcioğlu's musical compositions include:

• Passacaglia and Fugue for Orchestra, 1977.
• Trio for Piano, Cello and Violin. 1977.
• "Arı Kuşları", lied based on a poem by Atilla İlhan. 1977.
• Three pieces for piano, in D major, D-sharp minor, and F-sharp major(mp3, 1.9MB; nwc score, download player from here), 1975.
• Seninle Bir Dakika (A Minute with You), Turkey's 1975 entry to the Eurovision Song Contest. Here is the UK music magazine Melody Maker's report on the 1975 Eurovision event.
• Sonata Allegro for Piano. ca. 1969.(mp3, 9.5MB; nwc score).
• The Musical "Abdülgaffar," performed at Robert College, Istanbul, 1969.
• While at the Robert Academy High School, Istanbul, Ebcioğlu played the lead guitar in Optikler, the popular music band which won the first prize in the 1967 Milliyet Liselerarası Hafif Batı Müziği Yarışması (Popular Music Contest among High Schools, organized by the Milliyet Newspaper in Turkey). After the contest, Optikler released a 45 RPM record through the Sayan Plak record company, containing the tune Köylü Kızı (Country Girl) by Ebcioğlu (mp3, 2.2MB).

Other Information

Kemal Ebcioğlu was born in Ankara, Turkey. He is married, and has one daughter.

Dr. Ebcioğlu's present research interests include parallel scalable cloud computing and virtualization, high productivity exascale systems, overcoming the memory wall barrier, and dynamic binary translation and optimization.